044a77352f
NOTE: this feature is not ready for user testing, and not yet enabled in daily builds. It is being merged now for easier collaboration on development. HIP is a heterogenous compute interface allowing C++ code to be executed on GPUs similar to CUDA. It is intended to bring back AMD GPU rendering support on Windows and Linux. https://github.com/ROCm-Developer-Tools/HIP. As of the time of writing, it should compile and run on Linux with existing HIP compilers and driver runtimes. Publicly available compilers and drivers for Windows will come later. See task T91571 for more details on the current status and work remaining to be done. Credits: Sayak Biswas (AMD) Arya Rafii (AMD) Brian Savery (AMD) Differential Revision: https://developer.blender.org/D12578
88 lines
3.0 KiB
C++
88 lines
3.0 KiB
C++
/*
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* Copyright 2021 Blender Foundation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#pragma once
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CCL_NAMESPACE_BEGIN
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/* Given an array of states, build an array of indices for which the states
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* are active.
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*
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* Shared memory requirement is `sizeof(int) * (number_of_warps + 1)`. */
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#include "util/util_atomic.h"
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#ifdef __HIP__
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# define GPU_PARALLEL_ACTIVE_INDEX_DEFAULT_BLOCK_SIZE 1024
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#else
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# define GPU_PARALLEL_ACTIVE_INDEX_DEFAULT_BLOCK_SIZE 512
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#endif
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template<uint blocksize, typename IsActiveOp>
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__device__ void gpu_parallel_active_index_array(const uint num_states,
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int *indices,
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int *num_indices,
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IsActiveOp is_active_op)
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{
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extern ccl_gpu_shared int warp_offset[];
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const uint thread_index = ccl_gpu_thread_idx_x;
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const uint thread_warp = thread_index % ccl_gpu_warp_size;
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const uint warp_index = thread_index / ccl_gpu_warp_size;
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const uint num_warps = blocksize / ccl_gpu_warp_size;
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/* Test if state corresponding to this thread is active. */
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const uint state_index = ccl_gpu_block_idx_x * blocksize + thread_index;
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const uint is_active = (state_index < num_states) ? is_active_op(state_index) : 0;
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/* For each thread within a warp compute how many other active states precede it. */
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const uint thread_mask = 0xFFFFFFFF >> (ccl_gpu_warp_size - thread_warp);
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const uint thread_offset = ccl_gpu_popc(ccl_gpu_ballot(is_active) & thread_mask);
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/* Last thread in warp stores number of active states for each warp. */
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if (thread_warp == ccl_gpu_warp_size - 1) {
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warp_offset[warp_index] = thread_offset + is_active;
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}
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ccl_gpu_syncthreads();
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/* Last thread in block converts per-warp sizes to offsets, increments global size of
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* index array and gets offset to write to. */
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if (thread_index == blocksize - 1) {
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/* TODO: parallelize this. */
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int offset = 0;
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for (int i = 0; i < num_warps; i++) {
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int num_active = warp_offset[i];
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warp_offset[i] = offset;
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offset += num_active;
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}
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const uint block_num_active = warp_offset[warp_index] + thread_offset + is_active;
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warp_offset[num_warps] = atomic_fetch_and_add_uint32(num_indices, block_num_active);
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}
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ccl_gpu_syncthreads();
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/* Write to index array. */
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if (is_active) {
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const uint block_offset = warp_offset[num_warps];
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indices[block_offset + warp_offset[warp_index] + thread_offset] = state_index;
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}
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}
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CCL_NAMESPACE_END
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