Campbell Barton
f6fd3a84c2
- Nest compositor pages under the compositor module - Nest GUI, DNA/RNA & externformats modules under Blender. - Remove modules from intern which no longer exist. - Add intern modules (atomic, eigen, glew-mx, libc_compat, locale, numaapi, rigidbody, sky, utfconv). - Use 'intern_' prefix for intern modules since some of the modules use generic terms such as locale & atomic.
562 lines
16 KiB
C++
562 lines
16 KiB
C++
/*
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* Original code from jemalloc with this license:
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*
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* Copyright (C) 2002-2013 Jason Evans <jasone@canonware.com>.
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* All rights reserved.
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* Copyright (C) 2007-2012 Mozilla Foundation. All rights reserved.
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* Copyright (C) 2009-2013 Facebook, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice(s),
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice(s),
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER(S) ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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* EVENT SHALL THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*
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* The Original Code is Copyright (C) 2016 Blender Foundation.
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* All rights reserved.
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*
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* The Original Code is: adapted from jemalloc.
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*/
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/** \file
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* \ingroup intern_atomic
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*/
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#ifndef __ATOMIC_OPS_UNIX_H__
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#define __ATOMIC_OPS_UNIX_H__
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#include "atomic_ops_utils.h"
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#if defined(__arm__) || defined(__riscv)
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/* Attempt to fix compilation error on Debian armel and RISC-V kernels.
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* Both architectures do have both 32 and 64bit atomics, however
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* its gcc doesn't have __GCC_HAVE_SYNC_COMPARE_AND_SWAP_n defined.
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*/
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# define JE_FORCE_SYNC_COMPARE_AND_SWAP_1
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# define JE_FORCE_SYNC_COMPARE_AND_SWAP_2
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# define JE_FORCE_SYNC_COMPARE_AND_SWAP_4
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# define JE_FORCE_SYNC_COMPARE_AND_SWAP_8
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#endif
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/* Define the `ATOMIC_FORCE_USE_FALLBACK` to force lock-based fallback implementation to be used
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* (even on platforms where there is native implementation available via compiler.
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* Useful for development purposes. */
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#undef ATOMIC_FORCE_USE_FALLBACK
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/* -------------------------------------------------------------------- */
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/** \name Spin-lock implementation
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*
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* Used to implement atomics on unsupported platforms.
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* The spin implementation is shared for all platforms to make sure it compiles and tested.
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* \{ */
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typedef struct AtomicSpinLock {
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volatile int lock;
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/* Pad the structure size to a cache-line, to avoid unwanted sharing with other data. */
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int pad[32 - sizeof(int)];
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} __attribute__((aligned(32))) AtomicSpinLock;
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ATOMIC_INLINE void atomic_spin_lock(volatile AtomicSpinLock *lock)
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{
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while (__sync_lock_test_and_set(&lock->lock, 1)) {
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while (lock->lock) {
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}
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}
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}
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ATOMIC_INLINE void atomic_spin_unlock(volatile AtomicSpinLock *lock)
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{
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__sync_lock_release(&lock->lock);
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}
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/** \} */
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/* -------------------------------------------------------------------- */
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/** \name Common part of locking fallback implementation
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* \{ */
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/* Global lock, shared by all atomic operations implementations.
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*
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* Could be split into per-size locks, although added complexity and being more error-proone does
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* not seem to worth it for a fall-back implementation. */
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static _ATOMIC_MAYBE_UNUSED AtomicSpinLock _atomic_global_lock = {0};
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#define ATOMIC_LOCKING_OP_AND_FETCH_DEFINE(_type, _op_name, _op) \
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ATOMIC_INLINE _type##_t atomic_##_op_name##_and_fetch_##_type(_type##_t *p, _type##_t x) \
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{ \
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atomic_spin_lock(&_atomic_global_lock); \
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const _type##_t original_value = *(p); \
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const _type##_t new_value = original_value _op(x); \
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*(p) = new_value; \
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atomic_spin_unlock(&_atomic_global_lock); \
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return new_value; \
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}
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#define ATOMIC_LOCKING_FETCH_AND_OP_DEFINE(_type, _op_name, _op) \
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ATOMIC_INLINE _type##_t atomic_fetch_and_##_op_name##_##_type(_type##_t *p, _type##_t x) \
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{ \
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atomic_spin_lock(&_atomic_global_lock); \
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const _type##_t original_value = *(p); \
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*(p) = original_value _op(x); \
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atomic_spin_unlock(&_atomic_global_lock); \
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return original_value; \
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}
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#define ATOMIC_LOCKING_ADD_AND_FETCH_DEFINE(_type) \
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ATOMIC_LOCKING_OP_AND_FETCH_DEFINE(_type, add, +)
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#define ATOMIC_LOCKING_SUB_AND_FETCH_DEFINE(_type) \
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ATOMIC_LOCKING_OP_AND_FETCH_DEFINE(_type, sub, -)
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#define ATOMIC_LOCKING_FETCH_AND_ADD_DEFINE(_type) \
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ATOMIC_LOCKING_FETCH_AND_OP_DEFINE(_type, add, +)
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#define ATOMIC_LOCKING_FETCH_AND_SUB_DEFINE(_type) \
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ATOMIC_LOCKING_FETCH_AND_OP_DEFINE(_type, sub, -)
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#define ATOMIC_LOCKING_FETCH_AND_OR_DEFINE(_type) ATOMIC_LOCKING_FETCH_AND_OP_DEFINE(_type, or, |)
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#define ATOMIC_LOCKING_FETCH_AND_AND_DEFINE(_type) \
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ATOMIC_LOCKING_FETCH_AND_OP_DEFINE(_type, and, &)
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#define ATOMIC_LOCKING_CAS_DEFINE(_type) \
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ATOMIC_INLINE _type##_t atomic_cas_##_type(_type##_t *v, _type##_t old, _type##_t _new) \
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{ \
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atomic_spin_lock(&_atomic_global_lock); \
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const _type##_t original_value = *v; \
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if (*v == old) { \
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*v = _new; \
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} \
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atomic_spin_unlock(&_atomic_global_lock); \
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return original_value; \
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}
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/** \} */
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/* -------------------------------------------------------------------- */
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/** \name 64-bit operations
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* \{ */
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#if !defined(ATOMIC_FORCE_USE_FALLBACK) && \
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(defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8) || defined(JE_FORCE_SYNC_COMPARE_AND_SWAP_8))
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/* Unsigned */
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ATOMIC_INLINE uint64_t atomic_add_and_fetch_uint64(uint64_t *p, uint64_t x)
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{
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return __sync_add_and_fetch(p, x);
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}
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ATOMIC_INLINE uint64_t atomic_sub_and_fetch_uint64(uint64_t *p, uint64_t x)
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{
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return __sync_sub_and_fetch(p, x);
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}
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ATOMIC_INLINE uint64_t atomic_fetch_and_add_uint64(uint64_t *p, uint64_t x)
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{
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return __sync_fetch_and_add(p, x);
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}
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ATOMIC_INLINE uint64_t atomic_fetch_and_sub_uint64(uint64_t *p, uint64_t x)
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{
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return __sync_fetch_and_sub(p, x);
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}
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ATOMIC_INLINE uint64_t atomic_cas_uint64(uint64_t *v, uint64_t old, uint64_t _new)
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{
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return __sync_val_compare_and_swap(v, old, _new);
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}
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/* Signed */
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ATOMIC_INLINE int64_t atomic_add_and_fetch_int64(int64_t *p, int64_t x)
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{
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return __sync_add_and_fetch(p, x);
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}
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ATOMIC_INLINE int64_t atomic_sub_and_fetch_int64(int64_t *p, int64_t x)
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{
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return __sync_sub_and_fetch(p, x);
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}
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ATOMIC_INLINE int64_t atomic_fetch_and_add_int64(int64_t *p, int64_t x)
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{
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return __sync_fetch_and_add(p, x);
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}
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ATOMIC_INLINE int64_t atomic_fetch_and_sub_int64(int64_t *p, int64_t x)
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{
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return __sync_fetch_and_sub(p, x);
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}
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ATOMIC_INLINE int64_t atomic_cas_int64(int64_t *v, int64_t old, int64_t _new)
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{
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return __sync_val_compare_and_swap(v, old, _new);
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}
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#elif !defined(ATOMIC_FORCE_USE_FALLBACK) && (defined(__amd64__) || defined(__x86_64__))
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/* Unsigned */
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ATOMIC_INLINE uint64_t atomic_fetch_and_add_uint64(uint64_t *p, uint64_t x)
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{
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asm volatile("lock; xaddq %0, %1;"
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: "+r"(x), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return x;
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}
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ATOMIC_INLINE uint64_t atomic_fetch_and_sub_uint64(uint64_t *p, uint64_t x)
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{
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x = (uint64_t)(-(int64_t)x);
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asm volatile("lock; xaddq %0, %1;"
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: "+r"(x), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return x;
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}
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ATOMIC_INLINE uint64_t atomic_add_and_fetch_uint64(uint64_t *p, uint64_t x)
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{
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return atomic_fetch_and_add_uint64(p, x) + x;
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}
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ATOMIC_INLINE uint64_t atomic_sub_and_fetch_uint64(uint64_t *p, uint64_t x)
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{
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return atomic_fetch_and_sub_uint64(p, x) - x;
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}
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ATOMIC_INLINE uint64_t atomic_cas_uint64(uint64_t *v, uint64_t old, uint64_t _new)
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{
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uint64_t ret;
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asm volatile("lock; cmpxchgq %2,%1" : "=a"(ret), "+m"(*v) : "r"(_new), "0"(old) : "memory");
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return ret;
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}
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/* Signed */
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ATOMIC_INLINE int64_t atomic_fetch_and_add_int64(int64_t *p, int64_t x)
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{
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asm volatile("lock; xaddq %0, %1;"
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: "+r"(x), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return x;
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}
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ATOMIC_INLINE int64_t atomic_fetch_and_sub_int64(int64_t *p, int64_t x)
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{
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x = -x;
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asm volatile("lock; xaddq %0, %1;"
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: "+r"(x), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return x;
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}
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ATOMIC_INLINE int64_t atomic_add_and_fetch_int64(int64_t *p, int64_t x)
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{
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return atomic_fetch_and_add_int64(p, x) + x;
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}
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ATOMIC_INLINE int64_t atomic_sub_and_fetch_int64(int64_t *p, int64_t x)
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{
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return atomic_fetch_and_sub_int64(p, x) - x;
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}
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ATOMIC_INLINE int64_t atomic_cas_int64(int64_t *v, int64_t old, int64_t _new)
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{
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int64_t ret;
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asm volatile("lock; cmpxchgq %2,%1" : "=a"(ret), "+m"(*v) : "r"(_new), "0"(old) : "memory");
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return ret;
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}
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#else
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/* Unsigned */
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ATOMIC_LOCKING_ADD_AND_FETCH_DEFINE(uint64)
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ATOMIC_LOCKING_SUB_AND_FETCH_DEFINE(uint64)
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ATOMIC_LOCKING_FETCH_AND_ADD_DEFINE(uint64)
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ATOMIC_LOCKING_FETCH_AND_SUB_DEFINE(uint64)
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ATOMIC_LOCKING_CAS_DEFINE(uint64)
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/* Signed */
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ATOMIC_LOCKING_ADD_AND_FETCH_DEFINE(int64)
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ATOMIC_LOCKING_SUB_AND_FETCH_DEFINE(int64)
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ATOMIC_LOCKING_FETCH_AND_ADD_DEFINE(int64)
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ATOMIC_LOCKING_FETCH_AND_SUB_DEFINE(int64)
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ATOMIC_LOCKING_CAS_DEFINE(int64)
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#endif
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/** \} */
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/* -------------------------------------------------------------------- */
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/** \name 32-bit operations
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* \{ */
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#if !defined(ATOMIC_FORCE_USE_FALLBACK) && \
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(defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) || defined(JE_FORCE_SYNC_COMPARE_AND_SWAP_4))
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/* Unsigned */
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ATOMIC_INLINE uint32_t atomic_add_and_fetch_uint32(uint32_t *p, uint32_t x)
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{
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return __sync_add_and_fetch(p, x);
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}
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ATOMIC_INLINE uint32_t atomic_sub_and_fetch_uint32(uint32_t *p, uint32_t x)
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{
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return __sync_sub_and_fetch(p, x);
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}
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ATOMIC_INLINE uint32_t atomic_cas_uint32(uint32_t *v, uint32_t old, uint32_t _new)
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{
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return __sync_val_compare_and_swap(v, old, _new);
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}
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/* Signed */
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ATOMIC_INLINE int32_t atomic_add_and_fetch_int32(int32_t *p, int32_t x)
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{
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return __sync_add_and_fetch(p, x);
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}
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ATOMIC_INLINE int32_t atomic_sub_and_fetch_int32(int32_t *p, int32_t x)
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{
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return __sync_sub_and_fetch(p, x);
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}
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ATOMIC_INLINE int32_t atomic_cas_int32(int32_t *v, int32_t old, int32_t _new)
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{
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return __sync_val_compare_and_swap(v, old, _new);
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}
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#elif !defined(ATOMIC_FORCE_USE_FALLBACK) && \
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(defined(__i386__) || defined(__amd64__) || defined(__x86_64__))
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/* Unsigned */
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ATOMIC_INLINE uint32_t atomic_add_and_fetch_uint32(uint32_t *p, uint32_t x)
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{
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uint32_t ret = x;
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asm volatile("lock; xaddl %0, %1;"
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: "+r"(ret), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return ret + x;
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}
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ATOMIC_INLINE uint32_t atomic_sub_and_fetch_uint32(uint32_t *p, uint32_t x)
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{
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uint32_t ret = (uint32_t)(-(int32_t)x);
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asm volatile("lock; xaddl %0, %1;"
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: "+r"(ret), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return ret - x;
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}
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ATOMIC_INLINE uint32_t atomic_cas_uint32(uint32_t *v, uint32_t old, uint32_t _new)
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{
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uint32_t ret;
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asm volatile("lock; cmpxchgl %2,%1" : "=a"(ret), "+m"(*v) : "r"(_new), "0"(old) : "memory");
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return ret;
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}
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/* Signed */
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ATOMIC_INLINE int32_t atomic_add_and_fetch_int32(int32_t *p, int32_t x)
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{
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int32_t ret = x;
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asm volatile("lock; xaddl %0, %1;"
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: "+r"(ret), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return ret + x;
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}
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ATOMIC_INLINE int32_t atomic_sub_and_fetch_int32(int32_t *p, int32_t x)
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{
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int32_t ret = -x;
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asm volatile("lock; xaddl %0, %1;"
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: "+r"(ret), "=m"(*p) /* Outputs. */
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: "m"(*p) /* Inputs. */
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);
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return ret - x;
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}
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ATOMIC_INLINE int32_t atomic_cas_int32(int32_t *v, int32_t old, int32_t _new)
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{
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int32_t ret;
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asm volatile("lock; cmpxchgl %2,%1" : "=a"(ret), "+m"(*v) : "r"(_new), "0"(old) : "memory");
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return ret;
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}
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#else
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/* Unsigned */
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ATOMIC_LOCKING_ADD_AND_FETCH_DEFINE(uint32)
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ATOMIC_LOCKING_SUB_AND_FETCH_DEFINE(uint32)
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ATOMIC_LOCKING_CAS_DEFINE(uint32)
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/* Signed */
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ATOMIC_LOCKING_ADD_AND_FETCH_DEFINE(int32)
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ATOMIC_LOCKING_SUB_AND_FETCH_DEFINE(int32)
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ATOMIC_LOCKING_CAS_DEFINE(int32)
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#endif
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#if !defined(ATOMIC_FORCE_USE_FALLBACK) && \
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(defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4) || defined(JE_FORCE_SYNC_COMPARE_AND_SWAP_4))
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/* Unsigned */
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ATOMIC_INLINE uint32_t atomic_fetch_and_add_uint32(uint32_t *p, uint32_t x)
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{
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return __sync_fetch_and_add(p, x);
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}
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ATOMIC_INLINE uint32_t atomic_fetch_and_or_uint32(uint32_t *p, uint32_t x)
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{
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return __sync_fetch_and_or(p, x);
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}
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ATOMIC_INLINE uint32_t atomic_fetch_and_and_uint32(uint32_t *p, uint32_t x)
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{
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return __sync_fetch_and_and(p, x);
|
|
}
|
|
|
|
/* Signed */
|
|
ATOMIC_INLINE int32_t atomic_fetch_and_add_int32(int32_t *p, int32_t x)
|
|
{
|
|
return __sync_fetch_and_add(p, x);
|
|
}
|
|
|
|
ATOMIC_INLINE int32_t atomic_fetch_and_or_int32(int32_t *p, int32_t x)
|
|
{
|
|
return __sync_fetch_and_or(p, x);
|
|
}
|
|
|
|
ATOMIC_INLINE int32_t atomic_fetch_and_and_int32(int32_t *p, int32_t x)
|
|
{
|
|
return __sync_fetch_and_and(p, x);
|
|
}
|
|
|
|
#else
|
|
|
|
/* Unsigned */
|
|
ATOMIC_LOCKING_FETCH_AND_ADD_DEFINE(uint32)
|
|
ATOMIC_LOCKING_FETCH_AND_OR_DEFINE(uint32)
|
|
ATOMIC_LOCKING_FETCH_AND_AND_DEFINE(uint32)
|
|
|
|
/* Signed */
|
|
ATOMIC_LOCKING_FETCH_AND_ADD_DEFINE(int32)
|
|
ATOMIC_LOCKING_FETCH_AND_OR_DEFINE(int32)
|
|
ATOMIC_LOCKING_FETCH_AND_AND_DEFINE(int32)
|
|
|
|
#endif
|
|
|
|
/** \} */
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/** \name 16-bit operations
|
|
* \{ */
|
|
|
|
#if !defined(ATOMIC_FORCE_USE_FALLBACK) && \
|
|
(defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2) || defined(JE_FORCE_SYNC_COMPARE_AND_SWAP_2))
|
|
|
|
/* Signed */
|
|
ATOMIC_INLINE int16_t atomic_fetch_and_and_int16(int16_t *p, int16_t b)
|
|
{
|
|
return __sync_fetch_and_and(p, b);
|
|
}
|
|
ATOMIC_INLINE int16_t atomic_fetch_and_or_int16(int16_t *p, int16_t b)
|
|
{
|
|
return __sync_fetch_and_or(p, b);
|
|
}
|
|
|
|
#else
|
|
|
|
ATOMIC_LOCKING_FETCH_AND_AND_DEFINE(int16)
|
|
ATOMIC_LOCKING_FETCH_AND_OR_DEFINE(int16)
|
|
|
|
#endif
|
|
|
|
/** \} */
|
|
|
|
/* -------------------------------------------------------------------- */
|
|
/** \name 8-bit operations
|
|
* \{ */
|
|
|
|
#if !defined(ATOMIC_FORCE_USE_FALLBACK) && \
|
|
(defined(__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1) || defined(JE_FORCE_SYNC_COMPARE_AND_SWAP_1))
|
|
|
|
/* Unsigned */
|
|
ATOMIC_INLINE uint8_t atomic_fetch_and_and_uint8(uint8_t *p, uint8_t b)
|
|
{
|
|
return __sync_fetch_and_and(p, b);
|
|
}
|
|
ATOMIC_INLINE uint8_t atomic_fetch_and_or_uint8(uint8_t *p, uint8_t b)
|
|
{
|
|
return __sync_fetch_and_or(p, b);
|
|
}
|
|
|
|
/* Signed */
|
|
ATOMIC_INLINE int8_t atomic_fetch_and_and_int8(int8_t *p, int8_t b)
|
|
{
|
|
return __sync_fetch_and_and(p, b);
|
|
}
|
|
ATOMIC_INLINE int8_t atomic_fetch_and_or_int8(int8_t *p, int8_t b)
|
|
{
|
|
return __sync_fetch_and_or(p, b);
|
|
}
|
|
|
|
#else
|
|
|
|
/* Unsigned */
|
|
ATOMIC_LOCKING_FETCH_AND_AND_DEFINE(uint8)
|
|
ATOMIC_LOCKING_FETCH_AND_OR_DEFINE(uint8)
|
|
|
|
/* Signed */
|
|
ATOMIC_LOCKING_FETCH_AND_AND_DEFINE(int8)
|
|
ATOMIC_LOCKING_FETCH_AND_OR_DEFINE(int8)
|
|
|
|
#endif
|
|
|
|
/** \} */
|
|
|
|
#undef ATOMIC_LOCKING_OP_AND_FETCH_DEFINE
|
|
#undef ATOMIC_LOCKING_FETCH_AND_OP_DEFINE
|
|
#undef ATOMIC_LOCKING_ADD_AND_FETCH_DEFINE
|
|
#undef ATOMIC_LOCKING_SUB_AND_FETCH_DEFINE
|
|
#undef ATOMIC_LOCKING_FETCH_AND_ADD_DEFINE
|
|
#undef ATOMIC_LOCKING_FETCH_AND_SUB_DEFINE
|
|
#undef ATOMIC_LOCKING_FETCH_AND_OR_DEFINE
|
|
#undef ATOMIC_LOCKING_FETCH_AND_AND_DEFINE
|
|
#undef ATOMIC_LOCKING_CAS_DEFINE
|
|
|
|
#endif /* __ATOMIC_OPS_UNIX_H__ */
|