EEVEE-Next: Support for Intel ARC GPUs #113447

Merged
Jeroen Bakker merged 4 commits from Jeroen-Bakker/blender:eevee/intel-arc-support into main 2023-10-09 15:29:35 +02:00
4 changed files with 20 additions and 21 deletions
Showing only changes of commit 6ebc098bf9 - Show all commits

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@ -17,7 +17,7 @@
#define LUT_WORKGROUP_SIZE 16
/* Hierarchical Z down-sampling. */
#define HIZ_MIP_COUNT 1
#define HIZ_MIP_COUNT 6
/* NOTE: The shader is written to update 5 mipmaps using LDS. */
#define HIZ_GROUP_SIZE 32

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@ -38,12 +38,12 @@ void HiZBuffer::sync()
hiz_update_ps_.bind_ssbo("finished_tile_counter", atomic_tile_counter_);
hiz_update_ps_.bind_texture("depth_tx", &render_buffers.depth_tx, with_filter);
hiz_update_ps_.bind_image("out_mip_0", hiz_tx_.mip_view(0));
#if 0
hiz_update_ps_.bind_image("out_mip_1", hiz_tx_.mip_view(1));
hiz_update_ps_.bind_image("out_mip_2", hiz_tx_.mip_view(2));
hiz_update_ps_.bind_image("out_mip_3", hiz_tx_.mip_view(3));
hiz_update_ps_.bind_image("out_mip_4", hiz_tx_.mip_view(4));
hiz_update_ps_.bind_image("out_mip_5", hiz_tx_.mip_view(5));
#if 0
hiz_update_ps_.bind_image("out_mip_6", hiz_tx_.mip_view(6));
hiz_update_ps_.bind_image("out_mip_7", hiz_tx_.mip_view(7));
#endif

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@ -53,8 +53,6 @@ void main()
imageStore(out_mip_0, src_px + ivec2(1, 0), samp.zzzz);
imageStore(out_mip_0, src_px + ivec2(0, 0), samp.wwww);
}
}
#if 0
/* Level 1. (No load) */
float max_depth = max_v4(samp);
@ -66,19 +64,19 @@ void main()
bool active_thread;
int mask_shift = 1;
# define downsample_level(out_mip__, lod_) \
active_thread = all(lessThan(uvec2(local_px), gl_WorkGroupSize.xy >> uint(mask_shift))); \
barrier(); /* Wait for previous writes to finish. */ \
if (active_thread) { \
max_depth = max_v4(load_local_depths(local_px)); \
dst_px = ivec2((kernel_origin >> mask_shift) + local_px); \
imageStore(out_mip__, dst_px, vec4(max_depth)); \
} \
barrier(); /* Wait for previous reads to finish. */ \
if (active_thread) { \
store_local_depth(local_px, max_depth); \
} \
mask_shift++;
#define downsample_level(out_mip__, lod_) \
active_thread = all(lessThan(uvec2(local_px), gl_WorkGroupSize.xy >> uint(mask_shift))); \
barrier(); /* Wait for previous writes to finish. */ \
if (active_thread) { \
max_depth = max_v4(load_local_depths(local_px)); \
dst_px = ivec2((kernel_origin >> mask_shift) + local_px); \
imageStore(out_mip__, dst_px, vec4(max_depth)); \
} \
barrier(); /* Wait for previous reads to finish. */ \
if (active_thread) { \
store_local_depth(local_px, max_depth); \
} \
mask_shift++;
downsample_level(out_mip_2, 2);
downsample_level(out_mip_3, 3);
@ -94,6 +92,7 @@ void main()
}
finished_tile_counter = 0u;
#if 0
ivec2 iter = divide_ceil(imageSize(out_mip_5), ivec2(gl_WorkGroupSize.xy * 2u));
ivec2 image_border = imageSize(out_mip_5) - 1;
for (int y = 0; y < iter.y; y++) {
@ -123,5 +122,5 @@ void main()
// downsample_level(out_mip_10, 10);
}
}
}
#endif
#endif
}

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@ -15,12 +15,12 @@ GPU_SHADER_CREATE_INFO(eevee_hiz_update)
.storage_buf(0, Qualifier::READ_WRITE, "uint", "finished_tile_counter")
.sampler(0, ImageType::DEPTH_2D, "depth_tx")
.image(0, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_0")
#if 0
.image(1, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_1")
.image(2, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_2")
.image(3, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_3")
.image(4, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_4")
.image(5, GPU_R32F, Qualifier::READ_WRITE, ImageType::FLOAT_2D, "out_mip_5")
.image(5, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_5")
#if 0
.image(6, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_6")
.image(7, GPU_R32F, Qualifier::WRITE, ImageType::FLOAT_2D, "out_mip_7")
#endif